This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-211685, filed Jul. 12, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a large-scale integrated circuit device (to be referred to as an LSI hereinafter) having a clock frequency changing function and a computer system using the large-scale integrated circuit and a clock frequency changing method.
In a conventional LSI operated with a clock, in order to secure the operation under a high frequency, any one of the following three methods is employed:
I. method for supposing the worst conditions in design to determine a clock frequency;
II. method for selecting a chip operated at a high frequency in inspection after manufacturing;
III. method for attaching a sensor for measuring the temperature of an LSI in operation and for controlling an operation frequency with software to decrease the operation frequency when the LSI temperature raises over a predetermined temperature.
The method I is applied to a relatively small number of products such as ASIC (Application Specific Integrated Circuit) for specific applications.
The method II is frequently applied to a large number of products such as general-purpose memories and microprocessors.
The method III is used as a method for preventing a timing error by decreasing an operation frequency when an LSI cannot be cooled even though a cooling fan or the like is used in a notebook type personal computer or the like.
In the prior art, for example, design conditions are too severe in the method I, and an LSI is operated at a frequency lower than an upper limit of the operable frequency. As a result, the LSI must be used with operation performance lower than the actual capability (maximum value of an operation frequency).
The design conditions in the method II are milder than those in the method I. However, conditions such as a peripheral temperature and a power supply voltage are often severer than the real usage conditions, and an LSI must be used in a state in which operation performance is lower than the actual operation performance.
Even in the method III, although the peripheral temperature is considered, conditions such as a power supply voltage are often severer than the real usage conditions, and an LSI must be used in a state in which operation performance is lower than the actual operation performance.
In the conventional technique described above, in general, the practical maximum operation frequency of an LSI is fixedly determined every product within a range of performance lower than the maximum performance of the LSI.
On the other hand, as described in U.S. Pat. No. 5,872,907, the following technique is also proposed. That is, when an error caused by an AC timing error is detected in a fault tolerant type computer, a clock frequency is changed (decreased) to improve the reliability of the system.
In some personal computer or the like, a mechanism for multiplying an operation frequency of a processor or the like with a base clock of a system bus or the like by setting a register may be incorporated. In the mechanism of this type, a clock frequency is changed by using interruption while the system is operated in a stable condition.
According to the clock frequency changing technique, a computer (more-specifically, LSI) can be operated to achieve the actual capability of the computer (LSI). For this reason, the technique is useful to solve the problems. However, in an actual operation state, in order to stably operate the LSI to achieve the maximum performance, the clock frequency changing technique is not always sufficient.
Therefore, the present inventor proposes xe2x80x9cClock Generation Circuit and Clock Generation Methodxe2x80x9d which can changes a clock frequency in Japanese Patent Application No. 11-318771 (unpublished), so that an LSI to which the clock generation circuit (or the clock generation method) is applied is stably operated to achieve the maximum performance in an actual operation state.
However, in any clock frequency changing technique, a device for dynamically changing a clock frequency in a system operation in synchronism with another LSI (clock generation circuit included therein) is not considered.
Accordingly, it is an object of the present invention to provide an integrated circuit device having a clock frequency changing function which can dynamically change the frequency of a clock generated by the integrated circuit device in synchronism with another integrated circuit device, and a computer system having the integrated circuit device and a clock frequency changing method.
According to the present invention, there is provided an LSI which incorporates a clock generation circuit which can change a clock frequency, which is connected to a system bus and a clock control bus independent of the system bus together with another LSI, which operates in synchronous with the other LSI by the clock generated by the incorporated clock generation circuit, and which has a clock frequency changing function, including clock frequency changing means which dynamically executes changing of a clock frequency of the incorporated clock generation circuit by using at least the clock control bus in synchronism with another LSI.
When a computer system is configured such that a plurality of LSIs each having the above configuration are connected to the system bus and the clock control bus, by using the clock control bus for changing a clock frequency of every LSI, the clock frequency can be dynamically changed during system operation in synchronism with each other.
In order to change a clock frequency by using the clock control bus, at least the following two signals, i.e., a first signal representing that the clock frequency must be changed in a predetermined direction and a second signal representing that the clock frequency is changed in a direction opposing the direction of the first signal or that the clock frequency need not be changed are flowed through the clock control bus, and the clock frequency changing means includes clock state determination means for operating the first and second signals such that a present clock state can be designated, so that the clock frequency may be changed on the basis of the clock state designated by the first and second signals. When the clock state is represented by only the first and second signals, by a specific combination of the first signal representing that the change of the clock frequency is not unnecessary and the second signal representing that the clock frequency need not be changed in the predetermined direction, a clock state in which the clock frequency must be changed in the direction opposing the predetermined direction may be indicated. In addition, a third signal representing that the clock frequency must be changed in the direction opposing the predetermined direction may be added.
The system bus may also be used to change the clock frequency, and the clock frequency may be synchronously changed by using a bus transaction on the system bus. When the bus transaction on the system bus is used, a relatively high-speed clock can be controlled depending on the performance of the system bus.
In order to change the clock frequency by using the bus transaction on the system bus, the clock frequency changing means for an LSI serving as a master for a clock frequency changing operation using the bus transaction comprises:
means for detecting that a clock state which is represented by at least the first and second signals and which designates that a clock frequency must be changed is continued for a first number of clock cycles;
means for issuing the bus transaction for clock frequency changing to a target LSI of LSIs on the system bus and the clock control bus depending on the detection result of the detecting means; and
timing adjustment means for waiting until a second number of clock cycles elapse after a normal completion response notification from the target for the issued bus transaction.
The clock frequency is changed after the second number of clock cycles elapse.
The clock frequency changing means for an LSI serving as a target which changes a clock frequency by using the bus transaction comprises normal completion response means for notifying a master of a normal completion response of the bus transaction when the bus transaction for clock frequency changing is issued from an LSI serving as a master, if the clock frequency can be changed, upon completion of execution of the bus transaction; and timing adjustment means for waiting until a predetermined number of clock cycles elapse after the normal completion response notification.
The clock frequency may be changed after the predetermined number of clock cycles (second number of clock cycle counts) elapse.
The frequency changing means for another LSI except for the LSIs of a master and a target comprises timing adjustment means for waiting until a predetermined number of clock cycles elapse after a normal completion response notification of a bus transaction from the target to the master when the bus transaction for clock frequency changing is issued from the master, if the clock frequency can be changed.
The clock frequency may be changed after the predetermined number of clock cycles (second number of clock cycles) elapse.
In the above configuration, it can be easily realized that changing of the clock frequency is synchronously performed by using the bus transaction on the system bus between LSIs.
If retry response means for returning a retry response to the master in a predetermined phase when the clock frequency cannot be changed is added to the target clock frequency changing means, the clock frequency can be synchronously changed between LSIs by retrying a bus transaction even though a clock frequency cannot be changed in the target.
If changing disable notification means for notifying another LSI that the clock frequency cannot be changed by simultaneously asserting two predetermined signals on the system bus which are set in a state in which only one of the signals is asserted in a normal state or a state in which both the signals are deasserted when the clock frequency cannot be changed is added to a clock frequency changing means for another LSI except for the LSIs of the master and the target, another LSI can be notified that the clock frequency cannot be changed without a new special signal. For this reason, a bus transaction can be retried. A function of returning a retry response to the master even though the two predetermined signals are simultaneously asserted may be added to the retry response means of the target. In addition, a dedicated changing disable notification signal may be prepared.
In an LSI according to the present invention, in a configuration in which a clock frequency changing operation using a bus transaction on a system bus is not applied, the clock frequency changing means comprises:
means for detecting a specific state in which a clock state requiring a clock frequency changing operation continues for a first number of clock cycles; and
synchronization confirmation means for executing, at least once, an operation of confirming that clock frequency changing operations are synchronized with each other between the LSI and another LSI by operating at least the first or second signal at a predetermined timing when the specific state is detected by the detecting means and when the clock frequency can be changed.
The clock frequency is changed on the basis of the confirmation result of the synchronization confirmation means.
In the configuration described above, since it can be easily confirmed by using only a signal of the clock control bus that the clock frequency changing operations are synchronized with each other, synchronization of the clock changing operations can be secured by changing the clock frequency on the basis of the confirmation result. When a function of performing synchronization confirmation in the same manner as described above after the clock frequency is changed is added to the synchronization confirmation means, synchronization of the clock changing operations can be more reliably secured.
If the synchronization confirmation means comprises:
synchronization confirmation signal operation means for performing an operation of asserting at least one of the first and second signals at a predetermined first timing and then deasserting the asserted signal at a predetermined second timing when synchronization confirmation is executed once; and
timing detecting means for detecting the presence/absence of coincidence of an operation timing obtained by the synchronization confirmation signal operation means and operation timings obtained by the synchronization confirmation signal operation means of all other LSIs, and synchronization is confirmed depending on the timing coincidence detection performed by the timing detecting means, synchronization confirmation can be easily confirmed. However, in this method, since the signals of the clock control buses are simultaneously asserted and deasserted in all the LSIs, an increase in speed of the clock control bus is more different than an increase in speed of the system bus. For this reason, unlike the method for using a bus transaction on the system bus described above, this method is preferably applied to a frequency changing operation of a relatively low-speed clock. As a matter of course, when a clock control bus having a sufficiently high speed as compared with the clock frequency is used, the above limitation is withdrawn.
If the clock frequency changing means comprises:
frequency changing preparation incompletion notification signal operation means for operating at least one predetermined signal of the clock control bus to set a state representing clock frequency changing preparation incompletion when the clock frequency cannot be changed; and
clock frequency changing stop means for stopping a clock frequency changing operation when the clock frequency changing preparation incompletion is represented by an operation of the preparation incompletion notification signal operation means or an operation of a preparation incompletion notification signal operation means of another LSI, it is possible to stop the clock frequency changing operation when preparation for a clock frequency changing operation in any one of the LSIs connected to the system bus and the clock control bus is uncompleted. In this case, if, in place of the clock frequency changing stop means, clock frequency changing delaying means for delaying a clock frequency changing operation when clock frequency changing preparation incompletion is represented by an operation of the preparation incompletion notification signal operation means of its own LSI or another LSI, the clock frequency changing operation can be delayed when preparation for a clock frequency changing operation is uncompleted in any one of the LSIs connected to the system bus and the clock control bus. The delay time can be controlled by a duration of time of a state representing clock frequency changing preparation completion.
When a predetermined time or a time exceeding the predetermined time can be selected as the duration time of a state representing the clock frequency changing preparation incompletion, for example, the predetermined time represents that the clock frequency changing operation is stopped, and the time exceeding the predetermined time represents that the clock frequency changing operation is delayed by the time, so that the stop or delay of the clock frequency changing operation can also be selectively executed. In addition, a dedicated signal representing the clock frequency changing preparation incompletion can also be assigned as at least one predetermined signal described above. However, the specific states may be represented by using the first and second signals. For example, the clock frequency changing preparation incompletion may be represented by the first signal representing that the clock frequency need not be changed and the second signal representing the clock frequency changing preparation incompletion.
An LSI according to the present invention and having a clock frequency function includes:
a clock generation circuit;
means for issuing a bus transaction for clock frequency changing to the system bus when the usage right of the system bus can be acquired;
means for outputting a signal representing at least one of that a clock frequency is increased, that the clock frequency is decreased, and that the clock frequency is not changed to a clock control bus to notify another LSI connected to the system bus of a clock changing operation; and
means for controlling the clock generation circuit to execute a clock frequency changing operation after a predetermined number of clock cycles elapse when a retry request is not answered from another LSI connected to the system bus, and for keeping a signal on the clock control bus to the signal representing that the clock frequency changing operation is not performed.
Another LSI according to the present invention and having a clock frequency changing function comprises:
a clock generation circuit;
means for receiving a bus transaction, issued from an LSI which acquires the usage right of a system bus to the system bus, for changing a clock frequency;
means for receiving a signal representing at least one of that a clock frequency is increased, that the clock frequency is decreased, and that the clock frequency is not changed;
means for returning a normal response to the LSI which acquires the usage right of the system bus when it is determined that a notified clock changing operation can be performed in response to the bus transaction, for controlling the clock generation circuit to execute a clock frequency changing operation after a predetermined number of clock cycles elapse, and for keeping a signal on the clock control bus to the signal representing that the changing operation is not performed.
In the configuration as described above, clock frequency changing operations can be synchronously performed between LSIs by using both the clock control bus and the system bus.
A still another LSI according to the present invention and having a clock frequency changing function comprises:
a clock generation circuit;
means for monitoring at least first and second signals output to a clock control bus which is independent of a system bus;
means for deasserting the second signal when its own LSI completes preparation for a clock frequency changing operation and it is detected, because the first signal is not asserted, that another LSI connected to the system bus completes preparation for a clock changing operation, and for asserting the first signal to establish synchronization after a first cycle time elapses; and
means for deasserting the first signal to confirm that synchronous delay does not occur when a second cycle time elapses after the synchronization, and for controlling the clock generation circuit to execute a clock frequency changing operation when a third cycle time elapses after the synchronization.
A still another LSI according to the present invention and having a clock frequency changing function comprises:
a clock generation circuit;
means for monitoring at least one of first and second signals output to a clock control bus which is independent of a system bus;
means for determining that a clock frequency changing operation is requested when the first and second signals are asserted for a first cycle time, for asserting the first signal when preparation for the clock frequency changing operation is not completed, and for deasserting the first signal after a second cycle time elapses; and
means for detecting, because the second signal is not asserted in the second cycle time, that another LSI connected to the system bus is prepared for a clock frequency changing operation, for asserting the second signal a third cycle time after the first signal is deasserted, for deasserting the second signal after the fourth cycle time elapses, for confirming that synchronization is established and controlling the clock generation circuit to execute a clock frequency changing operation.
In the configuration, clock frequency changing operations can be synchronously performed between LSIs by using a clock control bus.
The present invention is also exemplified as an invention related to a computer system including a plurality of LSIs each having the above configuration, the plurality of LSIs being connected to each other by a system bus and a clock control bus. In the computer system, by adding a system monitor bus for connecting the plurality of LSIs to each other and a system monitor device, connected to the system monitor device, for detecting a difference between the clock frequencies of the LSIs by loading pieces of information for determining clock frequencies of the clock generation circuits incorporated in the LSIs and comparing the pieces of information, it can be secured that the set states of the clock frequencies are matched to each other in the entire system.
The present invention related to the computer system is also exemplified as an invention related to a method, i.e., a clock frequency changing method.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.